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Beschreibung Die STM32G431xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die alle die Einpräzisions-Datenverarbeitungsanweisungen des Arms und alle anderen Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU. Integrierte Hochgeschwindigkeitsspeicher (128 KByte Flash und 32 KByte SRAM), viele I/Os + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 2x 12-Bit-ADCs - 4x Komparatoren - 3x Operationsverstärker - 4x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 1x 32-Bit-Timer - 2x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit Low-Power-Timer - 3x I2Cs - 3x SPIs gemultiplext mit zwei halbduplexen I2Ss - 3 USARTs, 1x UART + 1x Low-Power-UART. - 1x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und der Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown - VBAT supply for RTC and backup registers . Clock management - 4 to 48 MHz crystal oscillator - 32 kHz oscillator with calibration - Internal 16 MHz RC with PLL option (± 1%) - Internal 32 kHz RC oscillator (± 5%) . Up to 86 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 12-channel DMA controller . 2 x ADCs 0.25 ìs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 4 x 12-bit DAC channels - 2 x buffered external channels 1 MSPS - 2 x unbuffered internal channels 15 MSPS . 4 x ultra-fast rail-to-rail analog comparators . 3 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 14 timers: - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer

Beschreibung Die STM32G441xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die die Einpräzisions-Datenverarbeitungsanweisungen des Arms und alle anderen Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU sowie ein AES. Integrierte Hochgeschwindigkeitsspeicher (128 KByte Flash und 32 KByte SRAM), viele I/Os + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 2x 12-Bit-ADCs - 4x Komparatoren - 3x Operationsverstärker - 4x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 1x 32-Bit-Timer - 2x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit Low-Power-Timer - 3x I2Cs - 3x SPIs gemultiplext mit zwei halbduplexen I2Ss - 3 USARTs, 1x UART + 1x Low-Power-UART. - 1x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und der Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown . Clock management - 4 to 48 MHz crystal oscillator - Internal 16 MHz RC with PLL option (± 1%) . Up to 86 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 12-channel DMA controller . 2 x ADCs 0.25 ìs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 4 x 12-bit DAC channels - 2 x buffered external channels 1 MSPS - 2 x unbuffered internal channels 15 MSPS . 4 x ultra-fast rail-to-rail analog comparators . 3 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 14 timers: - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer . Calendar RTC with alarm, periodic wakeup from stop/standby

Beschreibung Die STM32G441xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die die Einpräzisions-Datenverarbeitungsanweisungen des Arms und alle anderen Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU sowie ein AES. Integrierte Hochgeschwindigkeitsspeicher (128 KByte Flash und 32 KByte SRAM), viele I/Os + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 2x 12-Bit-ADCs - 4x Komparatoren - 3x Operationsverstärker - 4x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 1x 32-Bit-Timer - 2x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit Low-Power-Timer - 3x I2Cs - 3x SPIs gemultiplext mit zwei halbduplexen I2Ss - 3 USARTs, 1x UART + 1x Low-Power-UART. - 1x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und der Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown . Clock management - 4 to 48 MHz crystal oscillator - Internal 16 MHz RC with PLL option (± 1%) . Up to 86 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 12-channel DMA controller . 2 x ADCs 0.25 ìs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 4 x 12-bit DAC channels - 2 x buffered external channels 1 MSPS - 2 x unbuffered internal channels 15 MSPS . 4 x ultra-fast rail-to-rail analog comparators . 3 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 14 timers: - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer . Calendar RTC with alarm, periodic wakeup from stop/standby

Beschreibung Die STM32G484xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die die Single-Precision-Datenverarbeitungsanweisungen des Arms und alle Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU. Integrierte Hochgeschwindigkeitsspeicher (512 KByte Flash und 128 KByte SRAM), FSMC, Quad SPI Flash Speicherschnittstelle + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 5x 12-Bit-ADCs - 7x Komparatoren - 6x Operationsverstärker - 7x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 2x 32-Bit-Timer - 3x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit LP-Timer - 4x I2Cs - 4x SPIs multiplexed mit zwei halbduplexen I2Ss - 3 USARTs, 2x UART + 1x Low-Power-UART. - 3x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes - Routine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) - External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories - Quad-SPI memory interface . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown - VBAT supply for RTC and backup registers . Clock management - 4 to 48 MHz crystal oscillator - 32 kHz oscillator with calibration - Internal 16 MHz RC with PLL option (± 1%) - Internal 32 kHz RC oscillator (± 5%) . Up to 107 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 16-channel DMA controller . 25 x 12-bit ADCs 0.25 ìs, up to 42 channels. Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 7 x 12-bit DAC channels - 3 x buffered external channels 1 MSPS - 4 x unbuffered internal channels 15 MSPS . 7 x ultra-fast rail-to-rail analog comparators . 6 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 17 timers: - HRTIM (Hi-Resolution and complex waveform builder): 6 x16-bit counters, 184 ps resolution, 12 PWM - 2 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer . Calendar RTC with alarm, periodic wakeup from stop/standby . Communication interfaces - 3 x FDCAN controller supporting flexible data rat

Beschreibung Die STM32G441xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die die Einpräzisions-Datenverarbeitungsanweisungen des Arms und alle anderen Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU sowie ein AES. Integrierte Hochgeschwindigkeitsspeicher (128 KByte Flash und 32 KByte SRAM), viele I/Os + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 2x 12-Bit-ADCs - 4x Komparatoren - 3x Operationsverstärker - 4x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 1x 32-Bit-Timer - 2x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit Low-Power-Timer - 3x I2Cs - 3x SPIs gemultiplext mit zwei halbduplexen I2Ss - 3 USARTs, 1x UART + 1x Low-Power-UART. - 1x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und der Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown . Clock management - 4 to 48 MHz crystal oscillator - Internal 16 MHz RC with PLL option (± 1%) . Up to 86 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 12-channel DMA controller . 2 x ADCs 0.25 ìs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 4 x 12-bit DAC channels - 2 x buffered external channels 1 MSPS - 2 x unbuffered internal channels 15 MSPS . 4 x ultra-fast rail-to-rail analog comparators . 3 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 14 timers: - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer . Calendar RTC with alarm, periodic wakeup from stop/standby

Beschreibung Die STM32G441xx basieren auf dem leistungsstarken Arm Cortex-M4 32-Bit-RISC-Kern. Der Cortex-M4-Kern verfügt über eine Single-Precision-FPU, die die Einpräzisions-Datenverarbeitungsanweisungen des Arms und alle anderen Datentypen unterstützt. Implementiert ist ein vollständiger Satz von DSP Anweisungen und eine MPU sowie ein AES. Integrierte Hochgeschwindigkeitsspeicher (128 KByte Flash und 32 KByte SRAM), viele I/Os + Peripheriegeräten, die an 2 APB-Busse, 2 AHB-Busse und 1x 32-Bit-Multi-AHB-Busmatrix angeschlossen sind. Integrierte Schutzmechanismen für eingebettete Flash-Speicher + SRAM. Die Vorrichtungen beinhalten Peripheriegeräte, die eine mathematische/arithmetische Funktionsbeschleunigung ermöglichen. - 2x 12-Bit-ADCs - 4x Komparatoren - 3x Operationsverstärker - 4x DAC-Kanäle - 1x Spannungsreferenzpuffer - 1x RTC - 1x 32-Bit-Timer - 2x 16-Bit-PWM-Timer - 7x uni 16-Bit-Timer - 1x 16-Bit Low-Power-Timer - 3x I2Cs - 3x SPIs gemultiplext mit zwei halbduplexen I2Ss - 3 USARTs, 1x UART + 1x Low-Power-UART. - 1x FDCAN - 1x SAI - USB-Gerät - UCPD Einige unabhängige Stromversorgungen werden unterstützt, darunter ein analoger unabhängiger Versorgungseingang für ADC, DAC, OPAMPs und Komparatoren. Ein VBAT-Eingang ermöglicht die Sicherung der RTC und der Register. Features . Core: Arm 32-bit Cortex-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions . Operating conditions: - VDD, VDDA voltage range: 1.71 V to 3.6 V . Mathematical hardware accelerators - CORDIC for trigonometric functions acceleration - FMAC: Filter mathematical accelerator . Memories - 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP - 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes - Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM) . Reset and supply management - Power-on/power-down reset (POR/PDR/BOR) - Programmable voltage detector (PVD) - Low-power modes: sleep, stop, standby and shutdown . Clock management - 4 to 48 MHz crystal oscillator - Internal 16 MHz RC with PLL option (± 1%) . Up to 86 fast I/Os - All mappable on external interrupt vectors - Several I/Os with 5 V tolerant capability . Interconnect matrix . 12-channel DMA controller . 2 x ADCs 0.25 ìs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range . 4 x 12-bit DAC channels - 2 x buffered external channels 1 MSPS - 2 x unbuffered internal channels 15 MSPS . 4 x ultra-fast rail-to-rail analog comparators . 3 x operational amplifiers that can be used in PGA mode, all terminals accessible . Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.95 V) . 14 timers: - 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop - 1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop - 2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - 2 x watchdog timers (independent, window) - 1 x SysTick timer: 24-bit downcounter - 2 x 16-bit basic timers - 1 x low-power timer . Calendar RTC with alarm, periodic wakeup from stop/standby

The Art of Computer Programming is Knuth's multivolume analysis of algorithms. With the addition of this new volume, it continues to be the definitive description of classical computer science. Volume 4B, the sequel to Volume 4A, extends Knuth's exploration of combinatorial algorithms. These algorithms are of keen interest to software designers because ". . . a single good idea can save years or even centuries of computer time." The book begins with coverage of Backtrack Programming, together with a set of data structures whose links perform "delightful dances" and are ideally suited to this domain. New techniques for important applications such as optimum partitioning and layout are thereby developed. Knuth's writing is playful, and he includes dozens of puzzles to illustrate the algorithms and techniques, ranging from popular classics like edge-matching to more recent crazes like sudoku. Recreational mathematicians and computer scientists will not be disappointed! In the second half of the book, Knuth addresses Satisfiability, one of the most fundamental problems in all of computer science. Innovative techniques developed at the beginning of the twenty-first century have led to game-changing applications, for such things as optimum scheduling, circuit design, and hardware verification. Thanks to these tools, computers are able to solve practical problems involving millions of variables that only a few years ago were regarded as hopeless. The Mathematical Preliminaries Redux section of the book is a special treat, which presents basic techniques of probability theory that have become prominent since the original "preliminaries" were discussed in Volume 1. As in every volume of this remarkable series, the book includes hundreds of exercises that employ Knuth's ingenious rating system, making it easy for readers of varying degrees of mathematical training to find challenges suitable to them. Detailed answers are provided to facilitate self-study. "Professor Donald E. Knuth has always loved to solve problems. In Volume 4B he now promotes two brand new and practical general problem solvers, namely (0) the Dancing Links Backtracking and (1) the SAT Solver. To use them, a problem is defined declaratively (0) as a set of options, or (1) in Boolean formulae. Today's laptop computers, heavily armoured with very high speed processors and ultra large amounts of memory, are able to run either solver for problems having big input data. Each section of Volume 4B contains a multitudinous number of tough exercises which help make understanding surer. Happy reading!" --Eiiti Wada, an elder computer scientist, UTokyo "Donald Knuth may very well be a great master of the analysis of algorithms, but more than that, he is an incredible and tireless storyteller who always strikes the perfect balance between theory, practice, and fun. [ Volume 4B, Combinatorial Algorithms, Part 2 ] dives deep into the fascinating exploration of search spaces (which is quite like looking for a needle in a haystack or, even harder, to prove the absence of a needle in a haystack), where actions performed while moving forward must be meticulously undone when backtracking. It introduces us to the beauty of dancing links for removing and restoring the cells of a matrix in a dance which is both simple to implement and very efficient." --Christine Solnon, Department of Computer Science, INSA Lyon Register your book for convenient access to downloads, updates, and/or corrections as they become available.